1. Technical Field
The present invention relates generally to processors and computing systems, and more particularly, to multiprocessing systems and a circuit for early clock fault detection.
2. Description of the Related Art
Present-day high-speed processors typically use a lower frequency external clock source or resonant circuit that operates a lower frequency than the high-speed internal clock used to clock internal processor states. The internal clocks of some present-day processors exceed 2 GHz in frequency and therefore would present problematic distribution phase problems and radiate excessive electromagnetic interference (EMI) if provided from outside an integrated circuit package. Therefore, present-day processors typically employ a phase-lock loop (PLL) multiplier circuit to generate the high-frequency internal clock from a lower frequency external clock.
In multiprocessing systems, where many processors are connected and intercommunicate, often in an array or cube arrangement, a lower frequency clock is distributed to provide synchronized clocking of multiple processors so that bus communication may be supported quasi-asynchronously (i.e., without handshaking or a local bus clock). While providing an interconnect advantage, a failure of a clock driver or a clock interconnect supplying one of the processors can corrupt data and disrupt synchronized program execution of an entire system.
What is most critical is avoiding corruption of data in such a system, as invalid results may be produced in a system where a clock distribution element fails or the master clock fails and those results may be written to permanent storage or otherwise communicated outside of the multiprocessing system. A single missing external clock cycle can destroy synchronization in such a system, causing errors that propagate to fixed storage or other systems.
U.S. Pat. No. 6,466,058 describes a clock fault detection scheme that reference measures one phase of the output of a digital phase detector using the VCO output of the PLL and the a reference clock to which the VCO is locked. The counters are reset in response to the other phase out of the phase detector and flag an error if either of the two counters overflow. While the above described scheme will generate an error if either clock fails for a predetermined amount of time, such a scheme is insufficient for detecting faults that will cause the above-described multiprocessors to lose synchronization and generate errors.
It is therefore desirable to provide an early clock fault detection that can detect failure of master clock distribution in a multiprocessing system. It would further be desirable to provide early clock fault detection that can detect failure of master clock distribution within less than a single cycle of the master clock.